
`include "common_header.verilog"

//  *************************************************************************
//  File : p8264_latch.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2010 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Denis Poverennyy
//  info@morethanip.com
//  *************************************************************************
//  Description : The p8264_latch module is a Latched High (set with latch_set
//              and reset with latch_reset_sync)            
//  Version     : $Id: p8264_latch.v,v 1.1 2014/08/04 22:11:00 wt Exp $
//  *************************************************************************


module p8264_latch (

        reset_clk,
        clk,
        latch_reset_sync,
        latch_set,
        latched
                        );


input           reset_clk;              // async active high reset
input           clk;                    // clock
input           latch_reset_sync;       // synch latch reset
input           latch_set;              // latch set
output          latched;                // if 1, Latched High
//------------------------------------------------------
//              Output Signals
//------------------------------------------------------
reg             latched;         


always @( posedge clk or posedge reset_clk)
begin
        if ( reset_clk == 1'b1 )
        begin 
                latched  <= 1'b0;
        end
        else if (latch_reset_sync == 1'b1)
        begin                         
                latched  <= 1'b0;
        end                                          
        else if (latch_set == 1'b1)
        begin                         
                latched <= 1'b1;
        end                        
end


endmodule // module p8264_latch